1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device capable of storing multiple bits in one memory cell.
2. Description of the Related Art
Known non-volatile semiconductor memory devices include an NAND cell-type flash memory. The NAND cell-type flash memory comprises a memory cell array including a plurality of NAND cell units. An NAND cell unit includes a plurality of memory cells serially connected, and two selection transistors connected to both ends thereof. A memory cell in an erased state holds “1”-data with a negative threshold voltage. At the time of data write, electrons are injected into a floating gate, thereby rewriting the cell to hold “0”-data with a positive threshold voltage. The NAND cell-type flash memory is capable of shifting the threshold voltage only from a lower one to a higher one at the time of data write. The reverse shift (from a higher threshold voltage to a lower one) can be executed only in an erase operation on a block basis.
For the purpose of increasing the memory capacity in recent years, there has been developed the so-called multi-level NAND cell-type flash memory that can store information of two or more bits in one memory cell. If multi-level storage is executed in one memory cell provided with a plurality of threshold voltages, however, the more the value of multi-level storage is increased, the narrower the interval between adjacent threshold voltages becomes, resulting in an increased probability of erroneously reading out the stored information.
JP Patent No. 3165101 therefore discloses an invention in which multi-level data of multiple bits is divided into an upper bit group and a lower bit group such that error correction can be executed to each group. This is effective to execute error correction even if one memory cell is broken.
JP 2005-78721A on the other hand discloses an invention in which multi-level data of multiple bits is divided into an upper bit group and a lower bit group such that error correction can be executed to each group through different schemes. This invention focuses on a difference in the error probabilities between the upper bit group and the lower bit group contained in the multi-level data.